Designs of High-Speed Triple-Node-Upset Hardened Latch Based on Dual-Modular-Redundancy.

MLA

Huang, Zhengfeng, et al. “Designs of High-Speed Triple-Node-Upset Hardened Latch Based on Dual-Modular-Redundancy.” Journal of Circuits, Systems & Computers, vol. 33, no. 5, Mar. 2024, pp. 1–25. EBSCOhost, https://doi.org/10.1142/S0218126624500920.

APA

Huang, Z., Zhang, Y., Ai, L., Liang, H., Ni, T., Song, T., & Yan, A. (2024). Designs of High-Speed Triple-Node-Upset Hardened Latch Based on Dual-Modular-Redundancy. Journal of Circuits, Systems & Computers, 33(5), 1–25. https://doi.org/10.1142/S0218126624500920

Chicago

Huang, Zhengfeng, Yan Zhang, Lei Ai, Huaguo Liang, Tianming Ni, Tai Song, and Aibin Yan. 2024. “Designs of High-Speed Triple-Node-Upset Hardened Latch Based on Dual-Modular-Redundancy.” Journal of Circuits, Systems & Computers 33 (5): 1–25. doi:10.1142/S0218126624500920.