Analysis of PMOS logic two tail comparator for less power consumption compared with CMOS comparator.

The goal of this study is to create and evaluate new PMOS-based double tail comparators. We want to see how well they perform in comparison to a CMOS comparator, using VLSI technology. The comparator is created using a special computer program called the tanner tool. This software helps to mimic and test if the comparator is functioning properly. The power values we found came from altering the size of transistors. This research involved conducting 20 tests with various sizes. Both the control and experimental groups were tested with the same samples. The test's ability to detect differences was determined to be 80% using a software called G-power. The study found that the PMOS logic double tail comparator didn't use any units. The CMOS comparator didn't use any power. The number we got was zero. The number 0001 is important because it is too small to be considered statistically significant. In simple terms, the CMOS logic double tail comparator uses less electrical power than the PMOS double tail comparator. [ABSTRACT FROM AUTHOR]