A 0.5 V 10-bit SAR ADC with offset calibrated time-domain comparator.

This paper presents a low voltage energy-efficient 10-bit SAR ADC. A double-merge and split (DMAS) switching scheme is proposed to reduce the CDAC switching energy by 92.2 % compared with conventional one without extra reference voltage (V CM ). Gain tunable voltage-controlled delay unit (GT-VCDU) is proposed for offset calibration of time-domain comparator (TD-CMP). The residual offset is reduced by proposed stage-by-stage calibration. 1 sigma of TD-CMP offset is reduced to 0.8 mV. The SAR ADC is fabricated in the 55 nm CMOS process occupied a core area of 0.038 m m 2. With a supply voltage of 0.5 V and a Nyquist rate input, the prototype consumes 164 nW at 100kS/s. The ENOB is 8.86-bit, resulting a FoM of 3.53 fJ/conversion-step. [ABSTRACT FROM AUTHOR]