Design and performance analysis of CNTFET based ternary encoders for next generation communication systems.

In today's world, binary logic is implanted utilizing CMOS. However, CMOS has several drawbacks, including high leakage power and short channel effects. CNFET is used to implement ternary logics to avoid these drawbacks. The main benefit of ternary logic is that it takes up less space on the device and requires less memory. Half adder circuit for ternary logic is proposed in this study. To begin, a decoder is employed to convert ternary to binary signals. After going through a binary half adder, the binary signals are transformed to ternary using an encoder. The disadvantage of utilizing a simple encoder is that it has a low resistance route and so uses a lot of power. To address this, numerous encoders have been devised, including the basic encoder and the enhanced encoder. To save energy, encoders with low power consumption are employed. To eliminate latency, high-speed encoders are used. Variables such as chirality, diameter, pitch, number of tubes, oxide thickness, and dielectric materials are used to do a complete study of the encoder's power consumption and latency. This improved Encoder is used in conjunction with a half adder. [ABSTRACT FROM AUTHOR]