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Design of Low Power Area Efficient 2D FIR Filter Using Optimized Multiplier and Adder for Speech Signal Analysis.

Authors :
Shankar, B. Maruthi
Ramkumar, M.
Saravanan, V.
Source :
Circuits, Systems & Signal Processing. Sep2024, p1-26.
Publication Year :
2024

Abstract

In signal analysis, various filters, devices, or algorithms are utilized to process signals, selectively permitting or blocking frequencies to induce desired changes in signal properties. Speech analysis faces challenges dealing with accent, dialect, pitch, and non-stationary features. Filters are crucial in modifying frequency components, reducing noise impact, enhancing robustness, and improving efficiency in speech analyses. To tackle speech analysis challenges, a proposed solution involves a low power, area efficient 2D Finite Impulse Response (FIR) filter, utilizing optimized multipliers and adders. The design integrates the Hybrid Mountaineering Team Bowerbird Optimization Algorithm (HMTBOA) to optimize filter coefficients, minimizing switching activities while considering ripple contents, transition width parameters, and power requirements. Additionally, High Speed Approximate Parallel Prefix Adders<bold> (</bold>HSAPPA<bold>)</bold> and the adaptive banyan tree growth optimization algorithm aim to reduce path delay, enhance area efficiency, and lower design complexity and power consumption in approximate adder design and error efficient posit logarithm approximate multiplier. The suggested method achieves outstanding results, with a 3.05ns delay, 0.101mW power consumption, and a 26.36dB signal-to-noise ratio, highlighting its robustness and effectiveness in addressing signal analysis challenges. [ABSTRACT FROM AUTHOR]

Details

Language :
English
ISSN :
0278081X
Database :
Academic Search Index
Journal :
Circuits, Systems & Signal Processing
Publication Type :
Academic Journal
Accession number :
179930182
Full Text :
https://doi.org/10.1007/s00034-024-02870-4