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A Three-Dimensional Stacked Fin-CMOS. Technology for High-Density ULSI Circuits.
- Source :
-
IEEE Transactions on Electron Devices . Sep2005, Vol. 52 Issue 9, p1998-2003. 6p. - Publication Year :
- 2005
-
Abstract
- In this paper, a three-dimensional CMOS technology is proposed and implemented using stacked Fin-CMOS (SF-CMOS) architecture. The technology is based on a double layer silicon-on-insulator wafer formed by two oxygen implants to create two single-crystal silicon films with an oxide isolation layer in between. The proposed approach achieves a 50% area reduction and significant shortening of the wiring distance between active devices through vertical connection when compared with conventional planar CMOS technology. The SF-CMOS technology also inherits the scalability and two-dimensional processing compatibility of the FinFET structure. SF-CMOS devices and simple circuits were fabricated and characterized. [ABSTRACT FROM AUTHOR]
Details
- Language :
- English
- ISSN :
- 00189383
- Volume :
- 52
- Issue :
- 9
- Database :
- Academic Search Index
- Journal :
- IEEE Transactions on Electron Devices
- Publication Type :
- Academic Journal
- Accession number :
- 18087183
- Full Text :
- https://doi.org/10.1109/TED.2005.854267