PLD FAMILY BRIDGES FPGA AND CPLD NEEDS.

The article presents information on programmable-logic devices (PDL). Applications traditionally supported by high-density complex programmable-logic devices (CPLDs) and low-capacity field-programmable gate arrays (FPGA) now have another option, the MachXO series of logic devices. Developed by Lattice Semiconductor, the family brings lower cost and more features to the table. Lattice harnessed the efficiency of a logic architecture based on a lookup table and combined it with high-density, nonvolatile flash storage and distributed blocks of static memory. As a result, the MachXO devices shave cost by as much as 50 per cent per logic function. The MachXO series can handle many traditional FPGA and CPLD applications due in part to its on-chip distributed memory, a low-power sleep mode, and the ability to transparently update configuration data. Similar to the fabric in the company's XP series, the logic fabric consists of an array of programmable function units that each contains four logic slices. Each slice packs a pair of four-input lookup tables and the associated configuration SRAM. Such blocks perform logic, arithmetic, distributed RAM and distributed ROM functions.