Optimization of Threshold Voltage Window Under Tunneling Program/Erase in Nanocrystal Memories.

This paper analyzes solutions to improve the program/erase (PIE) window for nanocrystal (NC) memory cells, by means of the model presented in our previous work [1]. The limited threshold voltage (VT) window typically observed in the Fowler-Nordheim (FN) programming regime for NC memories was shown to be a direct consequence of the lack of any conduction and c mismatch between the tunnel and the interpoly-oxide at steady-state. This condition can be avoided when tunnel oxide conduction is due to direct tunneling, but to assure sufficiently short PIE times very thin oxides are required, sacrificing cell nonvolatility. The use of alternative materials for interpoly dielectric, gate and NC is investigated. Finally, barrier engineering is presented as a valid way to improve the available VT window. [ABSTRACT FROM AUTHOR]