Cite
Improvements in Polysilicon Etch Bias and Transistor Gate Control With Module Level APC Methodologies.
MLA
Williams, David A., et al. “Improvements in Polysilicon Etch Bias and Transistor Gate Control With Module Level APC Methodologies.” IEEE Transactions on Semiconductor Manufacturing, vol. 18, no. 4, Nov. 2005, pp. 522–27. EBSCOhost, https://doi.org/10.1109/TSM.2005.858490.
APA
Williams, D. A., Locander, A. R., Herrera, T., Garza, J. D., & Parker, C. K. (2005). Improvements in Polysilicon Etch Bias and Transistor Gate Control With Module Level APC Methodologies. IEEE Transactions on Semiconductor Manufacturing, 18(4), 522–527. https://doi.org/10.1109/TSM.2005.858490
Chicago
Williams, David A., Aaron R. Locander, Ted Herrera, John D. Garza, and Cynthia K. Parker. 2005. “Improvements in Polysilicon Etch Bias and Transistor Gate Control With Module Level APC Methodologies.” IEEE Transactions on Semiconductor Manufacturing 18 (4): 522–27. doi:10.1109/TSM.2005.858490.