Simultaneous multithreading trace processors: Improving trace processors performance

Abstract: Trace Processors is a promising next-generation microarchitecture that exploits implicit thread-level parallelism (TLP) in conventional applications by employing aggressive control and data speculation techniques. Although high performance can be achieved by trace processors, but in fact, processing element (PE) resources are still underutilized due to frequent trace cache misses and next-trace mispeculations. When trace cache miss occurs, trace dispatch engine must stall and supply nothing to idle PE until the completion of trace construction. When next-trace mispeculation occurs, in addition to trace dispatch engine stall, all speculative execution results after the mispeculated trace must be discarded. All the operations on those squashed traces are useless. When trace processors scales up with more PEs, this problem will become more severe. Addressing to this problem, we propose augmenting multiple thread contexts into trace processors. A combined microarchitecture—Simultaneous Multithreading trace processors (SMT trace processors) is proposed in this paper. By dispatching trace from other threads, the penalties of trace cache miss and next-trace mispeculation can be tolerated. Introducing multiple thread contexts reduce the percentage of wrong-path speculations for each thread and improve PE execution efficiency significantly. Simulation results show that integrating two thread contexts can improve 8-PE trace processors performance 27.7%. When augmenting four and eight thread contexts, the corresponding improvements are 28.7 and 15.4%. And we believe that even higher performance improvement can be expected when we integrate more PEs into SMT trace processors. [Copyright &y& Elsevier]