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A new successive approximation architecture for high-speed low-power ADCs
- Source :
-
AEU: International Journal of Electronics & Communications . Mar2006, Vol. 60 Issue 3, p217-223. 7p. - Publication Year :
- 2006
-
Abstract
- Abstract: A new high-speed successive approximation analog-to-digital converter (ADC) architecture is presented. Two-bits extraction in each clock cycle is the key idea to double the conversion speed. Generating reference levels for three comparators with only two digital-to-analog converter (DACs), is another novelty of the new architecture. The proposed DAC structure allows a substantial reduction in overall control logic complexity. A 10-bit 40Ms/S successive approximation ADC was designed based on the proposed architecture in CMOS technology. The simulation results show that the proposed architecture introduces 7% reduction in power consumption over conventional architecture. Furthermore, chip area for the new ADC is 40% less than what otherwise would be needed by an ADC using conventional architecture. [Copyright &y& Elsevier]
Details
- Language :
- English
- ISSN :
- 14348411
- Volume :
- 60
- Issue :
- 3
- Database :
- Academic Search Index
- Journal :
- AEU: International Journal of Electronics & Communications
- Publication Type :
- Academic Journal
- Accession number :
- 19697608
- Full Text :
- https://doi.org/10.1016/j.aeue.2005.03.006