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Universal test set for detecting stuck-at and bridging faults in double fixed-polarity Reed–Muller programmable logic arrays.
- Source :
-
IEE Proceedings -- Computers & Digital Techniques . Mar2006, Vol. 153 Issue 2, p109-116. 8p. 8 Diagrams, 3 Charts. - Publication Year :
- 2006
-
Abstract
- A testable design for detecting stuck-at and bridging faults in programmable logic arrays (PLAs) based on double fixed-polarity Reed–Muller (DFPRM) expression is presented. DFPRM expression has the advantage of compactness and easy testability. The EXOR part in the proposed structure is designed as a tree of depth (⌈log2s⌉+1), where s is the number of product terms and sum terms in the given DFPRM expression realised by PLAs. This solves an open problem of designing an EXOR-tree-based RMC network that admits a universal test set. For an n-variable function, a test sequence of length (2n+8) vectors is sufficient to detect all single stuck-at and bridging faults in the proposed design. The proposed EXOR-tree-based network reduces circuit delay significantly compared with cascaded EXOR-based design. The test sequence is independent of the function and the circuit-under-test, and the test set can be stored in a ROM for built-in-self-test. [ABSTRACT FROM AUTHOR]
Details
- Language :
- English
- ISSN :
- 13502387
- Volume :
- 153
- Issue :
- 2
- Database :
- Academic Search Index
- Journal :
- IEE Proceedings -- Computers & Digital Techniques
- Publication Type :
- Academic Journal
- Accession number :
- 20065672
- Full Text :
- https://doi.org/10.1049/ip-cdt:20050079