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Analysis and Modeling of Layout Scaling in Silicon Integrated Stacked Transformers.
- Source :
-
IEEE Transactions on Microwave Theory & Techniques . May2006, Vol. 54 Issue 5, p2203-2210. 8p. 2 Diagrams, 1 Chart, 16 Graphs. - Publication Year :
- 2006
-
Abstract
- The analysis and modeling of monolithic stacked transformers fabricated in a high-speed silicon bipolar technology is addressed. On-wafer experimental measurements are employed to investigate the effect of layout scaling on transformer performance parameters (i.e., self-resonance frequency, magnetic coupling coefficient, and insertion loss). Based on this analysis, a wideband lumped model is developed, whose parameters are related to layout and technological data through closed-form expressions. Model accuracy is demonstrated by comparing simulated and measured S-parameters, coil inductance, magnetic coupling coefficient, and maximum available gain of several transformers with scaled layout geometry. The self-resonance frequency is also employed as a figure-of-merit to demonstrate model accuracy at very high frequency. [ABSTRACT FROM AUTHOR]
Details
- Language :
- English
- ISSN :
- 00189480
- Volume :
- 54
- Issue :
- 5
- Database :
- Academic Search Index
- Journal :
- IEEE Transactions on Microwave Theory & Techniques
- Publication Type :
- Academic Journal
- Accession number :
- 21127621
- Full Text :
- https://doi.org/10.1109/TMTT.2006.872788