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Local silicon-gate carbon nanotube field effect transistors using silicon-on-insulator technology.

Authors :
Min Zhang
Chan, Philip C. H.
Yang Chai
Qi Liang
Tang, Z. K.
Source :
Applied Physics Letters. 7/10/2006, Vol. 89 Issue 2, p023116. 3p. 1 Diagram, 1 Chart, 2 Graphs.
Publication Year :
2006

Abstract

A local silicon-gate carbon nanotube field effect transistor (CNFET) configuration has been proposed and implemented for integration purpose. By combining the advantages of in situ carbon nanotube growth technology and the silicon-on-insulator technology, we have realized the CNFETs with individual device operation, low parasitic capacitance, high yield fabrication, and better compatibility to the complementary-metal-oxide-semiconductor (CMOS) process. The CNFETs show up-to-date electrical performance. The scaling effect of gate oxide is also explored. This configuration makes CNFET a step closer to the CMOS integrated circuit application. [ABSTRACT FROM AUTHOR]

Details

Language :
English
ISSN :
00036951
Volume :
89
Issue :
2
Database :
Academic Search Index
Journal :
Applied Physics Letters
Publication Type :
Academic Journal
Accession number :
21695343
Full Text :
https://doi.org/10.1063/1.2221515