Cite
Modeling and Analysis of Loading Effect on Leakage of Nanoscaled Bulk-CMOS Logic Circuits.
MLA
Mukhopadhyay, Saibal, et al. “Modeling and Analysis of Loading Effect on Leakage of Nanoscaled Bulk-CMOS Logic Circuits.” IEEE Transactions on Computer-Aided Design of Integrated Circuits & Systems, vol. 25, no. 8, Aug. 2006, pp. 1486–95. EBSCOhost, https://doi.org/10.1109/TCAD.2005.855934.
APA
Mukhopadhyay, S., Bhunia, S., & Roy, K. (2006). Modeling and Analysis of Loading Effect on Leakage of Nanoscaled Bulk-CMOS Logic Circuits. IEEE Transactions on Computer-Aided Design of Integrated Circuits & Systems, 25(8), 1486–1495. https://doi.org/10.1109/TCAD.2005.855934
Chicago
Mukhopadhyay, Saibal, Swarup Bhunia, and Kaushik Roy. 2006. “Modeling and Analysis of Loading Effect on Leakage of Nanoscaled Bulk-CMOS Logic Circuits.” IEEE Transactions on Computer-Aided Design of Integrated Circuits & Systems 25 (8): 1486–95. doi:10.1109/TCAD.2005.855934.