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Efficient and secure cryptographic systems based on addition chains: Hardware design vs. software/hardware co-design

Authors :
Nedjah, Nadia
de Macedo Mourelle, Luiza
Source :
Integration: The VLSI Journal. Jan2007, Vol. 40 Issue 1, p36-44. 9p.
Publication Year :
2007

Abstract

Abstract: Most of cryptographic systems are based on modular exponentiation, wherein the operands are considerably large. Generally, modular exponentiation is implemented using a chain of modular multiplications. One way of improving the throughput of a cryptographic system implementation is reducing the number of the required modular multiplications. Given the exponent, finding the minimal number of multiplications that are necessary to reach the exponentiation results is a hard problem. We take advantage of an evolutionary stochastic process, commonly called genetic algorithms, to compute minimal addition chains, allow us to reduce drastically the number of the required modular multiplications. In this paper, we investigate two different ways to implement modular exponentiation based on the evolved addition chain: the first approach consists of implementing all the exponentiation operation on hardware and the second approach combines software and hardware. While the first approach attempts to optimise the encryption/decryption throughput regardless of the cost of system implementation, the second attempts to reach a balance between the throughput and the cost of the implementation. [Copyright &y& Elsevier]

Details

Language :
English
ISSN :
01679260
Volume :
40
Issue :
1
Database :
Academic Search Index
Journal :
Integration: The VLSI Journal
Publication Type :
Academic Journal
Accession number :
22278281
Full Text :
https://doi.org/10.1016/j.vlsi.2005.12.010