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Reliability Comparison of Triple-Gate Versus Planar SOl FETs.
- Source :
-
IEEE Transactions on Electron Devices . Sep2006, Vol. 53 Issue 9, p2351-2357. 7p. 9 Black and White Photographs, 2 Diagrams, 11 Graphs. - Publication Year :
- 2006
-
Abstract
- A comparative study of the reliability issues of triple-gate and planar FETs processed on the same silicon-on-insulator wafer is presented. It is shown that the triple-gate architecture does not alter the behavior of the time-dependent dielectric breakdown (BD) for different gate voltages and temperatures. The apparent higher Weibull slope observed in planar devices with respect to the triple-gate devices is ascribed to the area dependence of the time-to-BD detection. In spite of the different surface orientations, low-frequency noise measurements indicate similar values of the interface trap density for triple-gate and planar FETs. [ABSTRACT FROM AUTHOR]
Details
- Language :
- English
- ISSN :
- 00189383
- Volume :
- 53
- Issue :
- 9
- Database :
- Academic Search Index
- Journal :
- IEEE Transactions on Electron Devices
- Publication Type :
- Academic Journal
- Accession number :
- 22676628
- Full Text :
- https://doi.org/10.1109/TED.2006.880824