Cite
Delay Modeling and Statistical Design of Pipelined Circuit Under Process Variation.
MLA
Datta, Animesh, et al. “Delay Modeling and Statistical Design of Pipelined Circuit Under Process Variation.” IEEE Transactions on Computer-Aided Design of Integrated Circuits & Systems, vol. 25, no. 11, Nov. 2006, pp. 2427–36. EBSCOhost, https://doi.org/10.1109/TCAD.2006.873886.
APA
Datta, A., Bhunia, S., Mukhopadhyay, S., & Roy, K. (2006). Delay Modeling and Statistical Design of Pipelined Circuit Under Process Variation. IEEE Transactions on Computer-Aided Design of Integrated Circuits & Systems, 25(11), 2427–2436. https://doi.org/10.1109/TCAD.2006.873886
Chicago
Datta, Animesh, Swarup Bhunia, Saibal Mukhopadhyay, and Kaushik Roy. 2006. “Delay Modeling and Statistical Design of Pipelined Circuit Under Process Variation.” IEEE Transactions on Computer-Aided Design of Integrated Circuits & Systems 25 (11): 2427–36. doi:10.1109/TCAD.2006.873886.