Scalable Matrix Multiplication With Hybrid CMOS-RSFQ Digital Signal Processor.

We report an RSFQ Digital Signal Processor design based on hybrid RSFQ-CMOS memory suitable for a general matrix-on-matrix multiplication algorithm. The DSP consists of an RSFQ Multiply-Accumulate Unit, memory caches and synchronization block, partitioned into multiple chips, and a large CMOS memory. The parameters of the RSFQ DSP are a 10 x 10 bits multiplication with rounding to 14 bits, an 18-bit accumulator length and a 3.7 Kb memory cache. The maximum simulated clock frequency is equal to 24 GHz for HYPRES 4.5 kA/cm2 process and optimum communication bandwidth with the CMOS memory is 2 Gbps. The simplified version of the RSFQ DSP consisting of a 4 x 4 MAC with rounding to 5 bits and 17 x 6 memory caches has been designed for HYPRES 4.5 kA/cm2 process. [ABSTRACT FROM AUTHOR]