Cite
Joint hardware–software leakage minimization approach for the register file of VLIW embedded architectures
MLA
Atienza, David, et al. “Joint Hardware–software Leakage Minimization Approach for the Register File of VLIW Embedded Architectures.” Integration: The VLSI Journal, vol. 41, no. 1, Jan. 2008, pp. 38–48. EBSCOhost, https://doi.org/10.1016/j.vlsi.2007.04.004.
APA
Atienza, D., Raghavan, P., Ayala, J. L., De Micheli, G., Catthoor, F., Verkest, D., & López-Vallejo, M. (2008). Joint hardware–software leakage minimization approach for the register file of VLIW embedded architectures. Integration: The VLSI Journal, 41(1), 38–48. https://doi.org/10.1016/j.vlsi.2007.04.004
Chicago
Atienza, David, Praveen Raghavan, José L. Ayala, Giovanni De Micheli, Francky Catthoor, Diederik Verkest, and Marisa López-Vallejo. 2008. “Joint Hardware–software Leakage Minimization Approach for the Register File of VLIW Embedded Architectures.” Integration: The VLSI Journal 41 (1): 38–48. doi:10.1016/j.vlsi.2007.04.004.