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Efficient Discrete-Time Bandpass Sigma-Delta Modulator and Digital I/Q Demodulator for Multistandard Wireless Applications.
- Source :
-
IEEE Transactions on Consumer Electronics . Feb2008, Vol. 54 Issue 1, p25-32. 8p. 5 Black and White Photographs, 9 Diagrams, 5 Charts, 4 Graphs. - Publication Year :
- 2008
-
Abstract
- This paper presents an ejJicient discrete-time bandpass sigma-delta (.ZA) modulator and digital in-phase /quadrature (I/Q) demodulator for multistandard wireless applications. The proposed bandpass IA modulator provides higher speed using advanced switched-capacitor resonators which are faster than the conventional ones. The test chip has been implemented in a 0.18 jim CMOS process and occupied with the active chip area of 0.16 mm2. The power consumption of the fabricated chip is 2.34 mWwith a 1.8 Vsupply voltage. The measured peak signal-to-noise ratios (SNR) are 34 dBfor 1.536 MHz (T-DMB), 26 dB for 5 MHz (UMTS), and 20 dB for 10MHz (WiBro) bandwidths, respectively. This paper also covers the simple and robust digital I/Q demodulator which has been realized using a field programmable gate array (FPGA) for digital signal processing'. [ABSTRACT FROM AUTHOR]
Details
- Language :
- English
- ISSN :
- 00983063
- Volume :
- 54
- Issue :
- 1
- Database :
- Academic Search Index
- Journal :
- IEEE Transactions on Consumer Electronics
- Publication Type :
- Academic Journal
- Accession number :
- 31300317
- Full Text :
- https://doi.org/10.1109/TCE.2008.4470019