Cite
A Selective Trigger Scan Architecture for VLSI Testing.
MLA
Hosseinabady, Mohammad, et al. “A Selective Trigger Scan Architecture for VLSI Testing.” IEEE Transactions on Computers, vol. 57, no. 3, Mar. 2008, pp. 316–28. EBSCOhost, https://doi.org/10.1109/TC.2007.70806.
APA
Hosseinabady, M., Sharifi, S., Lombardi, F., & Navabi, Z. (2008). A Selective Trigger Scan Architecture for VLSI Testing. IEEE Transactions on Computers, 57(3), 316–328. https://doi.org/10.1109/TC.2007.70806
Chicago
Hosseinabady, Mohammad, Shervin Sharifi, Fabrizio Lombardi, and Zainalabedin Navabi. 2008. “A Selective Trigger Scan Architecture for VLSI Testing.” IEEE Transactions on Computers 57 (3): 316–28. doi:10.1109/TC.2007.70806.