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Mixed hierarchical-functional fault models for targeting sequential cores
- Source :
-
Journal of Systems Architecture . Mar2008, Vol. 54 Issue 3/4, p465-477. 13p. - Publication Year :
- 2008
-
Abstract
- Abstract: Current work presents a set of fault models allowing high coverage for sequential cores in systems-on-a-chip. We propose a novel approach combining a hierarchical fault model for functional blocks, a functional fault model for multiplexers and a mixed hierarchical-functional fault model for comparison operators, respectively. The fault models are integrated into a fast high-level decision diagram based test path activation tool. According to the experiments, the proposed method significantly outperforms state-of-the-art test pattern generation tools. The main new contribution of this paper is a formal definition of high-level decision diagram representations and the combination of the three fault models in order to target high gate-level stuck-at fault coverage for sequential cores. [Copyright &y& Elsevier]
Details
- Language :
- English
- ISSN :
- 13837621
- Volume :
- 54
- Issue :
- 3/4
- Database :
- Academic Search Index
- Journal :
- Journal of Systems Architecture
- Publication Type :
- Academic Journal
- Accession number :
- 32054650
- Full Text :
- https://doi.org/10.1016/j.sysarc.2007.07.003