Cite
ON DESIGN AND APPLICATION MAPPING OF A NETWORK-ON-CHIP(NOC) ARCHITECTURE.
MLA
Jun Ho Bahn, et al. “On Design and Application Mapping of a Network-On-Chip(Noc) Architecture.” Parallel Processing Letters, vol. 18, no. 2, June 2008, pp. 239–55. EBSCOhost, https://doi.org/10.1142/S0129626408003363.
APA
Jun Ho Bahn, Seung Eun Lee, Yoon Seok Yang, Jungsook Yang, & Bagherzadeh, N. (2008). On Design and Application Mapping of a Network-On-Chip(Noc) Architecture. Parallel Processing Letters, 18(2), 239–255. https://doi.org/10.1142/S0129626408003363
Chicago
Jun Ho Bahn, Seung Eun Lee, Yoon Seok Yang, Jungsook Yang, and Nader Bagherzadeh. 2008. “On Design and Application Mapping of a Network-On-Chip(Noc) Architecture.” Parallel Processing Letters 18 (2): 239–55. doi:10.1142/S0129626408003363.