Cite
Word-Level Predicate-Abstraction and Refinement Techniques for Verifying RTL Verilog.
MLA
Jain, Himanshu, et al. “Word-Level Predicate-Abstraction and Refinement Techniques for Verifying RTL Verilog.” IEEE Transactions on Computer-Aided Design of Integrated Circuits & Systems, vol. 27, no. 2, Feb. 2008, pp. 366–79. EBSCOhost, https://doi.org/10.1109/TCAD.2007.907270.
APA
Jain, H., Kroening, D., Sharygina, N., & Clarke, E. M. (2008). Word-Level Predicate-Abstraction and Refinement Techniques for Verifying RTL Verilog. IEEE Transactions on Computer-Aided Design of Integrated Circuits & Systems, 27(2), 366–379. https://doi.org/10.1109/TCAD.2007.907270
Chicago
Jain, Himanshu, Daniel Kroening, Natasha Sharygina, and Edmund M. Clarke. 2008. “Word-Level Predicate-Abstraction and Refinement Techniques for Verifying RTL Verilog.” IEEE Transactions on Computer-Aided Design of Integrated Circuits & Systems 27 (2): 366–79. doi:10.1109/TCAD.2007.907270.