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A novel open-loop high-speed CMOS sample-and-hold
- Source :
-
AEU: International Journal of Electronics & Communications . Sep2008, Vol. 62 Issue 8, p588-596. 9p. - Publication Year :
- 2008
-
Abstract
- Abstract: A new open-loop high-speed CMOS sample-and-hold is presented. Based on new method for further reduction of voltage-dependent charge injection, a new CMOS sample-and-hold was designed. Simulation results confirm the effectiveness of this method. Over 10dB improvement in signal-to-noise ratio, compared to the signal-to-noise ratio of conventional bottom plate sampling S/Hs was achieved with this method. A comparison between newly designed S/H and the bottom-plate sampling S/H is presented. [Copyright &y& Elsevier]
Details
- Language :
- English
- ISSN :
- 14348411
- Volume :
- 62
- Issue :
- 8
- Database :
- Academic Search Index
- Journal :
- AEU: International Journal of Electronics & Communications
- Publication Type :
- Academic Journal
- Accession number :
- 33530935
- Full Text :
- https://doi.org/10.1016/j.aeue.2007.08.003