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Simplified Model Reference-Based Autotuning for Digitally Controlled SMPS.

Authors :
Corradini, Luca
Mattavelli, Paolo
Stefanutti, Walter
Saggini, Stefano
Source :
IEEE Transactions on Power Electronics. Jul2008, Vol. 23 Issue 4, p1956-1963. 8p. 3 Charts, 15 Graphs.
Publication Year :
2008

Abstract

This paper presents a closed-loop self-tuning technique for digitally controlled dc-dc switched-mode power supplies (SMPS) based on proportional-integral-derivative (PID) regulators, which derives from the more general model reference autotuning techniques. After briefly discussing an open loop, model-reference based tuning technique, a closed-loop solution is presented in which a perturbation frequency generated digitally is injected into the control loop and superimposed to the duty cycle command. The tuning is performed elaborating the signals right before and right after the injection point, and adjusting the PID parameters until predefined bandwidth and phase margin targets are obtained. The proposed approach allows for a robust and repeatable tuning, mainly because of the high resolution and dynamics available at the signal injection point. Moreover, the tuning is performed maintaining the closed-loop configuration, thus ensuring voltage regulation even during the PID adjustment, this being a fundamental constraint for most electronic equipments. The proposed technique is simple from the signal processing point of view, since it requires a few integrations, multiplications and phase-shift; further simplified implementations by employing nonsinusoidal perturbation waveforms like square-wave or triangular signals are also proposed. The approach is first discussed for two-parameters PI and PD regulators, and successively extended to PID structures, for which two possible implementations are proposed. The effectiveness of the tuning approach is verified by means of computer simulations and experimental tests carried out on a digital signal processor platform interfaced with a prototype point-of-load converter. The complexity of an HDL-implementation of the tuning hardware for field programmable gate array platforms is also discussed. [ABSTRACT FROM AUTHOR]

Details

Language :
English
ISSN :
08858993
Volume :
23
Issue :
4
Database :
Academic Search Index
Journal :
IEEE Transactions on Power Electronics
Publication Type :
Academic Journal
Accession number :
34752583
Full Text :
https://doi.org/10.1109/TPEL.2008.925419