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Fully Parallel Stochastic LDPC Decoders.
- Source :
-
IEEE Transactions on Signal Processing . Nov2008, Vol. 56 Issue 11, p5692-5703. 12p. 3 Black and White Photographs, 4 Diagrams, 4 Charts, 5 Graphs. - Publication Year :
- 2008
-
Abstract
- Stochastic decoding is a new approach to iterative decoding on graphs. This paper presents a hardware architecture for fully parallel stochastic low-density parity-check (LDPC) de- coders. To obtain the characteristics of the proposed architecture, we apply this architecture to decode an irregular state-of-the-art (1056,528) LDPC code on a Xilinx Virtex-4 LX200 field-pro- grammable gate-array (FPGA) device. The implemented decoder achieves a clock frequency of 222 MHz and a throughput of about 1.66 Gb/s at Eb/No = 4.25 dB (a bit error rate of 10-8). It provides decoding performance within 0.5 and 0.25 dB of the floating-point sum-product algorithm with 32 and 16 iterations, respectively, and similar error-floor behavior. The decoder uses less than 40% of the lookup tables, flip-flops, and 10 ports available on the FPGA device. The results provided in this paper validate the potential of stochastic LDPC decoding as a practical and competitive fully parallel decoding approach. [ABSTRACT FROM AUTHOR]
Details
- Language :
- English
- ISSN :
- 1053587X
- Volume :
- 56
- Issue :
- 11
- Database :
- Academic Search Index
- Journal :
- IEEE Transactions on Signal Processing
- Publication Type :
- Academic Journal
- Accession number :
- 35151318
- Full Text :
- https://doi.org/10.1109/TSP.2008.929671