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A novel low-power full-adder cell for low voltage
- Source :
-
Integration: The VLSI Journal . Sep2009, Vol. 42 Issue 4, p457-467. 11p. - Publication Year :
- 2009
-
Abstract
- Abstract: This paper presents a novel low-power majority function-based 1-bit full adder that uses MOS capacitors (MOSCAP) in its structure. It can work reliably at low supply voltage. In this design, the time-consuming XOR gates are eliminated. The circuits being studied are optimized for energy efficiency at 0.18-μm CMOS process technology. The adder cell is compared with seven widely used adders based on power consumption, speed, power-delay product (PDP) and area efficiency. Intensive simulation runs on a Cadence environment and HSPICE show that the new adder has more than 11% in power savings over a conventional 28-transistor CMOS adder. In addition, it consumes 30% less power than transmission function adder (TFA) and is 1.11 times faster. [Copyright &y& Elsevier]
Details
- Language :
- English
- ISSN :
- 01679260
- Volume :
- 42
- Issue :
- 4
- Database :
- Academic Search Index
- Journal :
- Integration: The VLSI Journal
- Publication Type :
- Academic Journal
- Accession number :
- 43609656
- Full Text :
- https://doi.org/10.1016/j.vlsi.2009.02.001