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Interface and electrical properties of La-silicate for direct contact of high-k with silicon

Authors :
Kakushima, K.
Tachi, K.
Adachi, M.
Okamoto, K.
Sato, S.
Song, J.
Kawanago, T.
Ahmet, P.
Tsutsui, K.
Sugii, N.
Hattori, T.
Iwai, H.
Source :
Solid-State Electronics. Jul2010, Vol. 54 Issue 7, p715-719. 5p.
Publication Year :
2010

Abstract

Abstract: Chemical bonding states and electrical characteristics of a La-silicate formed as a compositional transition layer at La2O3/Si interface has been examined. A direct contact of a high-k gate dielectric with Si substrate has been achieved without forming SiO2-based interfacial layer by forming a compositionally graded La-silicate layer, which is advantageous for equivalent oxide thickness (EOT) scaling. A transistor operation with an EOT of 0.48nm has been demonstrated with low temperature annealing, however a degradation of effective mobility (μ eff) has been observed. A high μ eff of 300cm2/Vs with relatively low interfacial state density (D it) of 1011 cm−2/eV can be achieved when annealed at 500°C, indicating fairly nice interface properties of silicate/Si substrate. Mobility analysis has revealed an additional Coulomb scattering below an EOT of 1.2nm, which is in good agreement with the negative shifts in threshold and flatband voltages. Moreover, increase in D it and subthreshold slope have been observed while decreasing the EOT, suggesting the influence of metal atoms diffused from the gate electrode. A mobility degradation model is proposed using metal induced defects generation. [Copyright &y& Elsevier]

Details

Language :
English
ISSN :
00381101
Volume :
54
Issue :
7
Database :
Academic Search Index
Journal :
Solid-State Electronics
Publication Type :
Academic Journal
Accession number :
50359810
Full Text :
https://doi.org/10.1016/j.sse.2010.03.005