Cite
Secure Testable S-box Architecture for Cryptographic Hardware Implementation.
MLA
Rahaman, H., et al. “Secure Testable S-Box Architecture for Cryptographic Hardware Implementation.” Computer Journal, vol. 53, no. 5, June 2010, pp. 581–91. EBSCOhost, https://doi.org/10.1093/comjnl/bxp048.
APA
Rahaman, H., Mathew, J., & Pradhan, D. K. (2010). Secure Testable S-box Architecture for Cryptographic Hardware Implementation. Computer Journal, 53(5), 581–591. https://doi.org/10.1093/comjnl/bxp048
Chicago
Rahaman, H., J. Mathew, and D. K. Pradhan. 2010. “Secure Testable S-Box Architecture for Cryptographic Hardware Implementation.” Computer Journal 53 (5): 581–91. doi:10.1093/comjnl/bxp048.