Cite
A Galois field-based logic synthesis with testability.
MLA
Mathew, J., et al. “A Galois Field-Based Logic Synthesis with Testability.” IET Computers & Digital Techniques (Institution of Engineering & Technology), vol. 4, no. 4, July 2010, pp. 263–73. EBSCOhost, https://doi.org/10.1049/iet-cdt.2009.0055.
APA
Mathew, J., Jabir, A. M., Singh, A. K., Rahaman, H., & Pradhan, D. K. (2010). A Galois field-based logic synthesis with testability. IET Computers & Digital Techniques (Institution of Engineering & Technology), 4(4), 263–273. https://doi.org/10.1049/iet-cdt.2009.0055
Chicago
Mathew, J., A. M. Jabir, A. K. Singh, H. Rahaman, and D. K. Pradhan. 2010. “A Galois Field-Based Logic Synthesis with Testability.” IET Computers & Digital Techniques (Institution of Engineering & Technology) 4 (4): 263–73. doi:10.1049/iet-cdt.2009.0055.