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Reconfigurable baseband processing architecture for communication.
- Source :
-
IET Computers & Digital Techniques (Institution of Engineering & Technology) . Jan2011, Vol. 5 Issue 1, p63-72. 10p. - Publication Year :
- 2011
-
Abstract
- The development of multiple communication standards and services has created the need for a flexible and efficient computational platform for baseband signal processing. Using a set of heterogeneous reconfigurable execution units (RCEUS) and a homogeneous control mechanism, the proposed reconfigurable architecture achieves a large computational capability while still providing a high degree of flexibility. Software tools and a library of commonly used algorithms are also proposed in this paper to provide a convenient framework for hardware generation and algorithm mapping. In this way, the architecture can be specified in a high-level language and it also provides increased hardware resource usage. Finally, we evaluate the system's performance on representative algorithms, specifically a 32-tap finite impulse response (FIR) filter and a 256-point fast Fourier transform (FFT), and compare them with commercial digital signal processor (DSP) chips as well as with other reconfigurable and multi-core architectures. [ABSTRACT FROM AUTHOR]
Details
- Language :
- English
- ISSN :
- 17518601
- Volume :
- 5
- Issue :
- 1
- Database :
- Academic Search Index
- Journal :
- IET Computers & Digital Techniques (Institution of Engineering & Technology)
- Publication Type :
- Academic Journal
- Accession number :
- 55983563
- Full Text :
- https://doi.org/10.1049/iet-cdt.2009.0121