Cite
An FPGA-Based Linear All-Digital Phase-Locked Loop.
MLA
Kumm, Martin, et al. “An FPGA-Based Linear All-Digital Phase-Locked Loop.” IEEE Transactions on Circuits & Systems. Part I: Regular Papers, vol. 57, no. 9, Sept. 2010, pp. 2487–97. EBSCOhost, https://doi.org/10.1109/TCSI.2010.2046237.
APA
Kumm, M., Klingbeil, H., & Zipf, P. (2010). An FPGA-Based Linear All-Digital Phase-Locked Loop. IEEE Transactions on Circuits & Systems. Part I: Regular Papers, 57(9), 2487–2497. https://doi.org/10.1109/TCSI.2010.2046237
Chicago
Kumm, Martin, Harald Klingbeil, and Peter Zipf. 2010. “An FPGA-Based Linear All-Digital Phase-Locked Loop.” IEEE Transactions on Circuits & Systems. Part I: Regular Papers 57 (9): 2487–97. doi:10.1109/TCSI.2010.2046237.