Power Optimization of an 11.75-Gb/s Combined Decision Feedback Equalizer and Clock Data Recovery Circuit in 0.18-\mu\m CMOS.

An 11.75-Gb/s combined decision feedback equalizer (DFE) and clock data recovery circuit in a 0.18-\mu\m CMOS is presented. Various techniques are applied to reduce the chip power consumption. In particular, the feedback path of the DFE is merged with an Alexander phase detector (PD). An analysis on the speed requirements of various blocks in the PD and DFE circuits is performed to determine the optimum power dissipation of each one. It is shown that the chip power consumption is reduced by 31% compared to a conventional design. The chip is capable of equalizing copper cable channels with up to 12-dB loss at the 5.875-GHz Nyquist frequency and consumes 101 mW (not including output buffers) with a 1.8-V supply voltage. [ABSTRACT FROM PUBLISHER]