Digital Calibration of Capacitor Mismatch in Sigma-Delta Modulators.

This paper presents a capacitor mismatch calibration technique in multibit discrete-time sigma-delta (\Sigma \Delta) modulators based on a capacitor error model, including nonideal integrator gain errors. This model enables the compensation of mismatch-induced nonlinear memory errors in conversion using a simple finite-impulse-response structure. Single-bit pseudorandom noise (PN) is utilized to identify the error coefficients, and an analog-domain PN removal technique is devised to minimize the input signal dynamic-range loss due to the PN circulation in the \Sigma \Delta loop. The behavioral simulation demonstrates that the proposed scheme effectively compensates for the multibit capacitor mismatch errors in the first- and second-order \Sigma \Delta modulators. [ABSTRACT FROM PUBLISHER]