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A 5 Gb/s Automatic Within-Pair Skew Compensator for Differential Data in 0.13 \mu\m CMOS.
- Source :
-
IEEE Transactions on Circuits & Systems. Part I: Regular Papers . Jun2011, Vol. 58 Issue 6, p1191-1202. 12p. - Publication Year :
- 2011
-
Abstract
- This paper presents an automatic within-pair skew compensator for high-speed differential data transmission. A wide-bandwidth data delay line is proposed to provide adjustable delay for data signals. Also presented is an on-chip within-pair skew detection circuit to detect skew between the differential data signals for automatic close-loop skew compensation. A within-pair skew compensator prototype for 5 Gb/s data was fabricated in 0.13 \mu\m CMOS. Measurement results show that the within-pair skew compensator can automatically compensate for within-pair skew of \pm200 ps (\pm1 unit interval). It consumes 20.4 mW from 1.2 V supply and occupies 0.015 \mm^2 die area. [ABSTRACT FROM PUBLISHER]
Details
- Language :
- English
- ISSN :
- 15498328
- Volume :
- 58
- Issue :
- 6
- Database :
- Academic Search Index
- Journal :
- IEEE Transactions on Circuits & Systems. Part I: Regular Papers
- Publication Type :
- Periodical
- Accession number :
- 62338670
- Full Text :
- https://doi.org/10.1109/TCSI.2010.2094317