On the Variability in Planar FDSOI Technology: From MOSFETs to SRAM Cells.

In this paper, an in-depth variability analysis, i.e., from the threshold voltage VT of metal–oxide–semiconductor field-effect-transistors (MOSFETs) to the static noise margin (SNM) of static random-access memory (SRAM) cells, is presented in fully depleted silicon-on-insulator (FDSOI) technology. The local VT variability \sigmaVT lower than AVT = \1.4\ \mV\cdot\mu\m is demonstrated. We investigated how this good VT variability is reported on the SNM fluctuations \sigmaSNM at the SRAM circuit level. It is found experimentally that \sigmaSNM is correlated directly to the \sigmaVT of SRAM transistors without any impact of the mean SNM value. The contributions of the individual MOSFETs in the SRAM cells have been determined quantitatively by using a homemade Simulation Program with Integrated Circuit Emphasis compact model calibrated on our FDSOI electrical characteristics. The VT variability in n-channel MOSFETs (nMOSFETs) is more critical than that in p-channel MOSFETs for SNM fluctuations, and \sigmaVT in drive nMOSFETs is the key parameter to control for minimizing \sigmaSNM. [ABSTRACT FROM PUBLISHER]