The Design and Characterization of a Half-Volt 32 nm Dual-Read 6T SRAM.

MLA

Kuang, Jente B., et al. “The Design and Characterization of a Half-Volt 32 Nm Dual-Read 6T SRAM.” IEEE Transactions on Circuits & Systems. Part I: Regular Papers, vol. 58, no. 9, Sept. 2011, pp. 2010–16. EBSCOhost, https://doi.org/10.1109/TCSI.2011.2162459.

APA

Kuang, J. B., Schaub, J. D., Gebara, F. H., Wendel, D., Frohnel, T., Saroop, S., Nassif, S., & Nowka, K. (2011). The Design and Characterization of a Half-Volt 32 nm Dual-Read 6T SRAM. IEEE Transactions on Circuits & Systems. Part I: Regular Papers, 58(9), 2010–2016. https://doi.org/10.1109/TCSI.2011.2162459

Chicago

Kuang, Jente B., Jeremy D. Schaub, Fadi H. Gebara, Dieter Wendel, Thomas Frohnel, Sudesh Saroop, Sani Nassif, and Kevin Nowka. 2011. “The Design and Characterization of a Half-Volt 32 Nm Dual-Read 6T SRAM.” IEEE Transactions on Circuits & Systems. Part I: Regular Papers 58 (9): 2010–16. doi:10.1109/TCSI.2011.2162459.