Tri-Mode Independent-Gate FinFETs for Dynamic Voltage/Frequency Scalable 6T SRAMs.

In this paper, we present tri-mode independent-gate (IG) FinFETs for dynamic voltage/frequency scalable 6T SRAMs. The proposed design exploits the fact that the spacer patterning technology, used for FinFET fabrication, offers the same device footprint for two- and one-fin transistors. The access transistor is designed for operation in three on-state modes achieving simultaneous increase in the read stability and write-ability and enabling appropriate tradeoffs between read stability and access time depending on the frequency requirements. The proposed design achieves 40%–48% higher weak-write test voltage and 2%–34% lower cell write time across a range of voltages compared with a conventional FinFET-based 6T SRAM under iso-leakage. During the read operation at high workload conditions (VDD = \0.7\ \V), 8% improvement in read static noise margin (SNM) is achieved with only 7% access time penalty. During the read operation at low workload conditions, 54%–75% improvement in the read SNM enables low voltage operation under process variations. The proposed IG FinFET SRAM achieves 125–136 mV lower VMIN across different global process corners at the cost of 15-mV higher retention VMIN. Iso-leakage comparison of the proposed technique with the previously proposed IG FinFET 6T SRAM is also performed. An increase in the cell area by 35% is observed compared to the minimum-sized conventional FinFET SRAM. However, there is no cell area penalty compared to the previously proposed IG FinFET SRAM. [ABSTRACT FROM PUBLISHER]