Cite
Memory and computation efficient hardware design for a 3 spatial and temporal layers SVC encoder.
MLA
Lee, Kyujoong, et al. “Memory and Computation Efficient Hardware Design for a 3 Spatial and Temporal Layers SVC Encoder.” IEEE Transactions on Consumer Electronics, vol. 57, no. 4, Nov. 2011, pp. 1921–28. EBSCOhost, https://doi.org/10.1109/TCE.2011.6131172.
APA
Lee, K., Rhee, C., Lee, H.-J., & Kang, J. (2011). Memory and computation efficient hardware design for a 3 spatial and temporal layers SVC encoder. IEEE Transactions on Consumer Electronics, 57(4), 1921–1928. https://doi.org/10.1109/TCE.2011.6131172
Chicago
Lee, Kyujoong, Chae Rhee, Hyuk-Jae Lee, and Jung Kang. 2011. “Memory and Computation Efficient Hardware Design for a 3 Spatial and Temporal Layers SVC Encoder.” IEEE Transactions on Consumer Electronics 57 (4): 1921–28. doi:10.1109/TCE.2011.6131172.