Back to Search
Start Over
Characterization and modeling of capacitances in FD-SOI devices
- Source :
-
Solid-State Electronics . May2012, Vol. 71, p53-57. 5p. - Publication Year :
- 2012
-
Abstract
- Abstract: Gate-to-channel capacitance C gc(Vg ) data obtained on FD-SOI MOS devices with gate lengths down to 35nm are first reported. Thus, a 2D numerical simulation procedure allowing to calculate the total device capacitance and parasitic capacitances is developed. This enabled us to discriminate the respective contributions of all parasitic components such as spacer, overlap, inner fringe and buried oxide capacitances in the structure. [Copyright &y& Elsevier]
Details
- Language :
- English
- ISSN :
- 00381101
- Volume :
- 71
- Database :
- Academic Search Index
- Journal :
- Solid-State Electronics
- Publication Type :
- Academic Journal
- Accession number :
- 73776384
- Full Text :
- https://doi.org/10.1016/j.sse.2011.10.020