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RTL planner automates logical to physical hierarchy transformation.

Authors :
Tuck, Barbara
Source :
Computer Design. Jun1998, Vol. 37 Issue 6, p24. 2p. 1 Diagram.
Publication Year :
1998

Abstract

Features the TeraForm RTL design planning software from Tera Systems. Applicability of the software in designing a system-on-a-chip; Automation of the creation of hierarchical, structured chips; Integration of TeraForm into the FlexStream deep-submicro ASIC-design flow; Communication of solution to back-end tools via constraint and command files.

Details

Language :
English
ISSN :
00104566
Volume :
37
Issue :
6
Database :
Academic Search Index
Journal :
Computer Design
Publication Type :
Periodical
Accession number :
750236