Design of an analog CMOS fuzzy logic controller chip

We propose an analog fuzzy logic controller chip structure in <f>1.2 μm</f> CMOS technology. It employs a new architecture for fuzzifier circuit that generates membership functions with a very suitable range and precision. These membership functions are simply tunable by setting some voltages on IC pins. Input has three membership functions and output is five singleton membership functions. Also, a novel defuzzifier circuit is used which occupies a small chip area. The controller is tested for two inputs, one output, and nine tunable fuzzy rules. The proposed architecture has an operation speed of <f>6.25 MFLIPS</f> (<f>6.25×106</f> fuzzy logic inference per second) and power consumption of <f>16.3 mW</f>. The whole chip area is less than <f>0.7 mm2</f> which is very small. Simulation tests show a good functionality of controller in response to some inputs to confirm the success of the design. The application of the system to the synthesis of a second-order system in a feedback loop is also considered. [Copyright &y& Elsevier]