A 75-dB SNDR, 5-MHz Bandwidth Stage-Shared 2–2 MASH \Delta \Sigma Modulator Dissipating 16 mW Power.

This paper presents a new stage-sharing technique in a discrete-time (DT) 2–2 MASH delta-sigma (\Delta \Sigma) ADC to reduce the modulator power consumption and chip die area. The proposed technique shares all active blocks between the two stages of the modulator. The 2–2 MASH modulator utilizes the second-order Chain of Integrators with Weighted Feed-forward Summation (CIFF) and the Cascade of Integrators with Distributed Feedback Branches (CIFB) architectures for the first and second stages, respectively. Using the proposed technique, the second integrator and the adder op-amps of the modulator first stage are shared with the first and second integrator op-amps of the second stage. In addition to the stage-sharing scheme, other changes are introduced to improve the modulator dynamic range (DR) and power dissipation. Measurement results show that the modulator designed in a 0.13∼\mum CMOS technology achieves 75 dB SNDR over a 5 MHz signal bandwidth with a clock frequency of 130 MHz, while dissipating less than 9 mW analog power. [ABSTRACT FROM AUTHOR]