Performance, Metastability, and Soft-Error Robustness Trade-offs for Flip-Flops in 40 nm CMOS.

MLA

Rennie, David, et al. “Performance, Metastability, and Soft-Error Robustness Trade-Offs for Flip-Flops in 40 Nm CMOS.” IEEE Transactions on Circuits & Systems. Part I: Regular Papers, vol. 59, no. 8, Aug. 2012, pp. 1626–34. EBSCOhost, https://doi.org/10.1109/TCSI.2012.2206505.

APA

Rennie, D., Li, D., Sachdev, M., Bhuva, B. L., Jagannathan, S., Wen, S., & Wong, R. (2012). Performance, Metastability, and Soft-Error Robustness Trade-offs for Flip-Flops in 40 nm CMOS. IEEE Transactions on Circuits & Systems. Part I: Regular Papers, 59(8), 1626–1634. https://doi.org/10.1109/TCSI.2012.2206505

Chicago

Rennie, David, David Li, Manoj Sachdev, Bharat L. Bhuva, Srikanth Jagannathan, ShiJie Wen, and Richard Wong. 2012. “Performance, Metastability, and Soft-Error Robustness Trade-Offs for Flip-Flops in 40 Nm CMOS.” IEEE Transactions on Circuits & Systems. Part I: Regular Papers 59 (8): 1626–34. doi:10.1109/TCSI.2012.2206505.