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Process Variation Tolerant All-Digital 90^\circ Phase Shift DLL for DDR3 Interface.
- Source :
-
IEEE Transactions on Circuits & Systems. Part I: Regular Papers . Oct2012, Vol. 59 Issue 10, p2186-2196. 11p. - Publication Year :
- 2012
-
Abstract
- An all-digital 90^\circ phase shift delay lock loop (DLL) is presented, which is robust against the delay mismatch caused by process variation. Each of the four 90^\circ phase shift blocks accurately aligns its output to a 90^\circ shifted phase using its own ring oscillator and locking delay code. It is analytically proved that the phase shift accuracy of the proposed 90^\circ phase shift block is always higher than that of the conventional all-digital 90^\circ phase shift DLL. The harmonic locking problem is prevented by a ring oscillator and a counter. An area-efficient binary-to-thermometer converter is proposed to reduce the area overhead caused by the delay-line control logic. A fast operating frequency with a finer resolution is achieved through the fine delay range selector and the resistance controlled fine delay unit. The proposed 90^\circ phase shift DLL is implemented using a 45-nm CMOS process. The phase shift accuracy errors at the 90^\circ and 270^\circ phases are 0.43^\circ and 1.01^\circ, respectively, when the maximum locking delay code difference between the four 90^\circ phase shift delay lines corresponds to \pm 9.97^\circ at 800 MHz. It proves that the DLL corrects the significant phase error caused by process variation. The power consumption is 3.3 mW at 800 MHz. [ABSTRACT FROM AUTHOR]
Details
- Language :
- English
- ISSN :
- 15498328
- Volume :
- 59
- Issue :
- 10
- Database :
- Academic Search Index
- Journal :
- IEEE Transactions on Circuits & Systems. Part I: Regular Papers
- Publication Type :
- Periodical
- Accession number :
- 82707004
- Full Text :
- https://doi.org/10.1109/TCSI.2012.2188943