Cite
Power-Rail ESD Clamp Circuit With Ultralow Standby Leakage Current and High Area Efficiency in Nanometer CMOS Technology.
MLA
Yeh, Chih-Ting, and Ming-Dou Ker. “Power-Rail ESD Clamp Circuit With Ultralow Standby Leakage Current and High Area Efficiency in Nanometer CMOS Technology.” IEEE Transactions on Electron Devices, vol. 59, no. 10, Oct. 2012, pp. 2626–34. EBSCOhost, https://doi.org/10.1109/TED.2012.2209120.
APA
Yeh, C.-T., & Ker, M.-D. (2012). Power-Rail ESD Clamp Circuit With Ultralow Standby Leakage Current and High Area Efficiency in Nanometer CMOS Technology. IEEE Transactions on Electron Devices, 59(10), 2626–2634. https://doi.org/10.1109/TED.2012.2209120
Chicago
Yeh, Chih-Ting, and Ming-Dou Ker. 2012. “Power-Rail ESD Clamp Circuit With Ultralow Standby Leakage Current and High Area Efficiency in Nanometer CMOS Technology.” IEEE Transactions on Electron Devices 59 (10): 2626–34. doi:10.1109/TED.2012.2209120.