Multi-standard S Σ Δ Modulator for GSM/WCDMA Applications.

This paper reports the design of multi-standard sigma delta modulator with low power consideration. It uses the cascaded methodology for modulator design to reduce power dissipation and single feedback system has been used to provide higher stability. The concept of oversampling and noise shaping is used in the design of modulator to increase Signal to Noise Ratio (SNR). The OP-AMP designed has a gain of 62 dB and phase margin of 72° to make the design stable. The second order sigma delta modulator designed can be used for either GSM or WCDMA applications at a sampling frequency of 5 MHz and 20 MHz, respectively. The bandwidth of the signal considered for GSM and WCDMA is 200 KHz and 2 MHz, respectively. The SNR and dynamic range obtained for GSM is 82 dB and 71 dB, respectively, and for WCDMA the same is 62 dB and 54 dB, respectively. The multi-standard modulator is designed in standard 180 nm CMOS technology at a power supply of 1.8 V and the total power consumed is 4.867 mW. [ABSTRACT FROM AUTHOR]