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An 8-bit Integrate-and-Sample Receiver for Rate-Scalable Photonic Analog-to-Digital Conversion.
- Source :
-
IEEE Transactions on Microwave Theory & Techniques . Dec2012 Part 1, Vol. 60 Issue 12, p3798-3809. 12p. - Publication Year :
- 2012
-
Abstract
- Jitter limitations pose significant challenges for high-resolution and sampling-rate analog-to-digital converters (ADCs). This paper describes an integrate-and-sample (IAS) receiver suitable for use in an optical parametric photonic ADC. Rate-scalable photonic-sampling techniques provide low-jitter optical sampling and analog-to-digital conversion of the wideband signal up to 10 GHz and beyond. An 8-bit 2-GS/s IAS receive channel is described for a rate-scalable photonic ADC. Electronic measurements are shown for an RF tone and a photonic Gaussian pulse source and compared to simulations. A two-channel IAS array is fabricated in a 120-nm SiGe BiCMOS process and packaged onto a printed circuit board for integration into the photonic-sampling setup. A single 2-GS/s channel achieves a measured performance higher than 8.1 ENOB. The two-channel integrated circuit consumes 890 mA per channel from 5- and 2.5-V supplies and occupies an area of \ 1.6\times \ 2.0~\ mm^2. [ABSTRACT FROM AUTHOR]
Details
- Language :
- English
- ISSN :
- 00189480
- Volume :
- 60
- Issue :
- 12
- Database :
- Academic Search Index
- Journal :
- IEEE Transactions on Microwave Theory & Techniques
- Publication Type :
- Academic Journal
- Accession number :
- 84489430
- Full Text :
- https://doi.org/10.1109/TMTT.2012.2222042